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Creators/Authors contains: "Aghasi, Hamidreza"

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  1. Free, publicly-accessible full text available January 1, 2026
  2. Free, publicly-accessible full text available January 1, 2026
  3. Bonizzoni, Edoardo (Ed.)
    This brief presents an ultra-low-power class-D voltage-controlled oscillator (VCO) designed for GHz applications that mandate decent phase noise performance. A waveform-centric approach of phase noise reduction by controlling the ratio between the floating and single-ended (SE) capacitors in an oscillator tank is proposed. By co-designing an RF choke with the tank inductor to introduce high impedance for the floating capacitors, the optimum capacitance ratio is maintained across the tuning range. The VCO is fabricated in 65nm Bulk CMOS technology and achieves a measured phase noise of -118.36 dBc/Hz and -138.64 dBc/Hz, and figure-of-merit of 192.89 dBc/Hz and 194.52 dBc/Hz at 1 MHz and 10 MHz offset frequencies, respectively. The VCO’s lowest measured 1/f3 corner is approximately 50kHz, which enables a decent figure-of-merit (FoM) down to a frequency offset of 10 kHz. The VCO features a tuning range of 40% (3.1 GHz -4.66 GHz) using a one-bit switch to realize two-point modulation in phase-locked loops (PLLs) with milliwatt-level power consumption. 
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  4. TPC of IEEE ESSCIRC Conference (Ed.)
    This paper presents an mmWave FMCW radar that can achieve sub-centimeter-scale range resolution at 14- GHz chirp-bandwidth while maintaining the radar range beyond 50 meters. To meet the requirements on power efficiency, chirp linearity, and signal-to-noise ratio (SNR), a phase-locked steppedchirp FMCW radar architecture is introduced. Specifically, a fully integrated radar transceiver comprising an interleaved frequency-segmented phase-locked transmitter and a segmented receiver architecture with high sensitivity is presented. The proposed design addresses the limitations of conventional typeII phase-locked loops (PLLs) in extending the radar bandwidth across multiple sub-bands with identical chirp profiles. Fabricated in a 22nm FD-SOI technology, the prototype chip comprises two sub-bands with 14 GHz of free-running bandwidth and 10 GHz of phase-locked bandwidth. The system achieves -101.7 dBc/Hz phase noise at 1 MHz offset, 8 dBm of effective isotropic radiated power (EIRP), 10 dB noise figure (NF), and 362.6 mW collective power consumption of transmitter and receiver arrays. 
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